Expected: Cadence Will Add RTL Generation to ChipStack in Q4
Cadence has announced a natural-language workflow for generating and refining RTL, but access is still limited to an expected early-access release for selected customers.
Edited by Tyronne Panaino
Cadence announced on September 22 that it plans to add an RTL Generation Agent to the ChipStack AI Super Agent, with selected customers expected to receive early access in the fourth quarter of 2026. The new workflow is aimed at chip-design teams that want to turn high-level specifications into RTL, revise existing RTL and evaluate power, performance and area earlier in front-end development.
The material change is scope. Cadence says ChipStack is moving beyond autonomous verification and debugging into RTL creation and refinement. That could shorten the path from a design requirement to an implementation candidate, but the announcement is not a general-availability release. It describes an expected, restricted rollout and reports early results from Cadence-led evaluations rather than an independently reproduced production record.
What is known
Cadence describes ChipStack as a hierarchy in which a super agent coordinates task-specific agents that use the company's electronic design automation tools. For the new workflow, a user can provide a high-level specification through natural-language prompts, while the agents generate RTL, analyse it and refine the result against power, performance and area targets. The same announcement adds a route for updating existing RTL when architecture, functionality or PPA requirements change.
This is a broader job than producing code-like text. Cadence says the workflow connects generation to its analysis, verification and signoff-grade technologies. The practical promise is therefore an iterative loop: translate a requirement into RTL, measure the design against engineering targets, revise it and keep verification inside the workflow. The announcement does not document which interfaces, design languages or project sizes will be supported in the first release.
Honda R&D is evaluating the agent on advanced automotive system-on-chip work. Cadence presents that collaboration as early customer validation, not as a completed deployment across a production portfolio. The source does not publish Honda's test set, acceptance thresholds, schedule or a before-and-after result that outside teams can inspect.
What Cadence's early results do and do not show
Cadence reports an average 24% reduction in area and an 18% reduction in power against pure foundation-model code generation, while saying the tested RTL remained fully functionally accurate. Those figures are useful as a description of the vendor's development target, but they are not enough to establish a general performance level. The announcement does not state how many designs were tested, how complex they were, which baseline model produced the comparison RTL or whether an independent party reproduced the measurements.
The comparison is also narrower than the full engineering decision. Teams adopting the agent will still need evidence that generated or revised RTL satisfies their own functional, power, timing, area, security and process requirements. Cadence's emphasis on connecting agents to established EDA tools makes that verification boundary central to the product proposition; it does not remove the need to validate each design.
Expected availability and likely user impact
Cadence expects the expanded ChipStack and InnoStack capabilities to reach selected early-access customers during the fourth quarter of 2026. The company has not supplied a specific launch day, pricing, eligibility rules or a timetable for broader availability. Until those details appear, engineering groups should treat the announcement as a roadmap checkpoint rather than a tool they can assume is available in their environment today.
If the early-access product matches the announced workflow, front-end teams could use it for two bounded tasks: producing an initial RTL candidate from a specification and applying requirement-driven updates to an existing design. The value will depend on how well Cadence exposes the verification trail, constraints and human approval points around those changes. A polished generated result is less important than a result engineers can inspect, test and carry through their established design process.
What would confirm it
The next verifiable checkpoint is a dated early-access release with product documentation showing supported inputs, interfaces, languages, access conditions and the exact handoff into Cadence analysis and signoff tools. Reproducible evaluation details, results across multiple design classes and customer evidence beyond a vendor announcement would help readers judge whether the reported PPA improvements transfer to real projects. A broader availability notice would be required before describing the agent as generally released.
Status
Expectation. Cadence has confirmed the product announcement and its intended workflow, while the Q4 select-customer release remains prospective. Internal confidence is medium because the evidence is a single interested first-party source and the reported evaluation has not been independently reproduced.
Sources
Update note: Last reviewed 2026-09-28. We will revise this post when Cadence documents early-access availability, supported workflows or independently checkable evaluation details.
Sources
- Cadence press release — official
Drafted with AI assistance from source briefs; reviewed for citation completeness and label accuracy.