SK Hynix Shows HBF, PIM and SALT-KV for AI Inference Memory
The chipmaker's summit showcase maps flash, processing-in-memory and semantic cache tiering to different inference bottlenecks, without yet providing commercial availability dates.
Edited by Tyronne Panaino
SK Hynix showcased three approaches to AI inference memory at AI Infra Summit 2026 on September 17: High Bandwidth Flash, processing-in-memory hardware and SALT-KV software for tiering model cache data. The company presented the technologies as a portfolio for workloads that no longer fit neatly inside a GPU-plus-HBM design.
The event confirmed that SK Hynix is developing and demonstrating the components, but it did not establish commercial availability, customer deployments or independently measured performance. For AI-system designers, the useful signal is the architecture: the company is trying to match different memory and storage technologies to the access pattern and latency needs of each inference workload.
HBF targets the space between HBM and SSDs
High Bandwidth Flash is SK Hynix's proposed intermediate memory tier. It applies through-silicon-via packaging to NAND flash, aiming to combine more capacity than high-bandwidth memory with more bandwidth than conventional solid-state storage. The company displayed a structural model rather than announcing a shipping product.
That positioning is tied to long-context and agent workloads, where a large working set can make it expensive to keep every token-related state in the fastest memory. HBF is intended to create another placement option between scarce HBM capacity and slower, larger SSD pools. The source does not provide a measured latency, bandwidth, power or price comparison, so the size of that advantage remains unverified.
PIM brings selected computation into memory
SK Hynix also displayed its AiM chip, an AiMX accelerator card and a server equipped with that card. The underlying processing-in-memory approach puts some computational functions inside memory hardware to reduce movement between a processor and memory. At the summit, visitors could try an LLM service running on the displayed system.
This is a different bottleneck from HBF. HBF adds a capacity-and-bandwidth tier, while PIM attempts to reduce how much data must travel through the conventional processor-memory path. SK Hynix says that can improve performance and power efficiency for fast-decoding workloads, but the event report offers no independent benchmark or production workload data.
SALT-KV manages cache placement across tiers
SALT-KV, short for Semantic-Aware Lifecycle Tiering for KV Cache, operates at the software and data-placement layer. It divides an LLM's key-value cache into context-based segments, assesses reuse value and storage cost, and assigns those segments to HBM, DRAM or SSD. SK Hynix demonstrated the system with a server using one of its enterprise SSDs and an LLM-based game.
The idea is to reserve the fastest and most expensive memory for cache segments likely to be reused while moving lower-value material to larger, slower tiers. That can matter as conversations lengthen or agents accumulate more tasks, because the cache records earlier attention computations and grows with the working context. The demonstration shows the concept running; it does not prove how the policy behaves across models, serving stacks or failure conditions.
What changed from the usual memory story
The three technologies address separate constraints rather than presenting one replacement for HBM. HBF adds another hardware tier, PIM changes where some computation happens, and SALT-KV decides where cache data should live. That portfolio framing is more specific than a general promise to supply more memory for AI accelerators.
It is still a roadmap and demonstration signal. SK Hynix did not provide release dates, qualified system partners, pricing, production volumes or reproducible performance results for the showcased stack. The next verifiable checkpoints are product specifications, sampling or shipment notices, and external system measurements.
Status
Confirmed. SK Hynix documented the summit showcase and the functions it assigns to HBF, PIM/AiMX and SALT-KV; availability and performance remain unverified vendor claims.
Sources
Update note: Last reviewed 2026-09-22. We will revise this post when SK Hynix publishes availability, detailed specifications or independently testable performance evidence.
Sources
- SK Hynix Newsroom — official
Drafted with AI assistance from source briefs; reviewed for citation completeness and label accuracy.